1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
An element isolation technique called STI (Shallow Trench Isolation) is used with an increase in integration density of a conventional semiconductor device.
In the element isolation technique, a trench is formed in a surface of a semiconductor substrate, and the trench is filled with an element isolation film to isolate a plurality of element forming regions from each other.
However, in the semiconductor device using such an element isolation technique, it is known that a hump characteristic is exhibited, as shown in FIG. 6. FIG. 6 is a diagram showing a relationship between a gate electrode and a drain current.
An impurity in the element forming region is diffused in the element isolation film, and an impurity concentration is lowered in the element forming region close to the element isolation film. A gate oxide film on a boundary between the element forming region and the element isolation film becomes thin. Due to this, a threshold voltage of a channel region close to the element isolation film is lower than a threshold voltage of an original channel. For this reason, a parasitic transistor is formed. In the semiconductor device, it can be regarded that two transistors which are equivalently different in threshold voltage from each other. In this manner, it is considered that a hump characteristic as shown in FIG. 6 is generated. The reference symbol A in FIG. 6 denotes a curve showing a relationship between a gate voltage and a drain current in a main transistor, the reference symbol B denotes a curve showing a relationship between a gate voltage and a drain current in a parasitic transistor, and the reference symbol C denotes a curve obtained by combining the curves A and B.
In order to suppress generation of the hump characteristic, a semiconductor device 800 as shown in FIG. 7 is known (see Japanese Patent Application Laid-Open (JP-A) No. 2004-288873), for example.
In the semiconductor device 800, an end portion of a gate electrode 801 is configured with a first gate line portion 801A and a second gate line portion 801B. A region 802 sandwiched between the first gate line portion 801A and the second gate line portion 801B is used as a p-type semiconductor region. In the semiconductor device 800, a source region 803 and a drain region 804 are n-type semiconductor regions.
In the semiconductor device 800, a channel region is disconnected by the p-type semiconductor region 802, and a parasitic transistor can be prevented from being formed.
The semiconductor device 900 shown in FIG. 8 is also proposed (see JP-A No. 2001-148478).
In the semiconductor device 900, a first high-resistance region 903 is formed between a source region 901 and an element isolation film 902, and a second high-resistance region 905 is formed between a drain region 904 and an element isolation film 902. In this case, for example, the source region 901 and the drain region 904 are n+-type diffusion layers, and the first high-resistance region 903 and the second high-resistance region 905 are n−-type diffusion layers or p−-type diffusion layers.
The first high-resistance region 903 and the second high-resistance region 905 are formed so that the channel region and the boundary between the element isolation film 902 and the element forming region do not overlap. Accordingly, hump characteristic generation can be suppressed.
However, in the technique of JP-A No. 2004-288873, since an end portion of the gate electrode 801 is configured with the first gate line portion 801A and the second gate line portion 801B, the shape of the gate electrode 801 is complicated.
In the technique of JP-A No. 2001-148478, when each of the first high-resistance region 903 and the second high-resistance region 905 is formed by an n−-type diffusion layer, an inter-drain-source current may flow through a channel region of a parasitic transistor disadvantageously.
On the other hand, the first high-resistance region 903 and the second high-resistance region 905 are configured by a p−-type diffusion layer, the following problems may occur.
Since the first high-resistance region 903 is arranged adjacent to the source region 901, a contact metal film may be provided over the first high-resistance region 903 and the source region 901, and the same voltage as that in the source region 901 is applied to the first high-resistance region 903.
Similarly, a contact metal film is formed over the second high-resistance region 905 and the drain region 904, the same voltage as in the drain region 904 is applied to the second high-resistance region 905.
For this reason, a potential of the first high-resistance region 903 is equal to a potential of the source region 901, and a potential of the second high-resistance region 905 is equal to a potential of the drain region 904. Although a substrate potential can be made equal to the potential of the source region 901, since the substrate potential is different from the potential of the drain region 904, a leakage current may flow over the second high-resistance region 905 formed on the drain region 904 side and a p-type semiconductor substrate.
In JP-A No. 2001-148478, the high-resistance regions 903 and 905 are arranged on the source region 901 side and the drain region 904 side, respectively, to reduce an area of an element forming region. For this reason, in the configuration of JP-A No. 2001-148478, the high-resistance regions 903 and 905 are necessarily arranged on the source region 901 side and the drain region 904 side, respectively.